Representations and Methodology of Future Computing Technologies

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Molecular scale computing, Nanotechnology, as well as Quantum computing are trends in future computing that might offer the way to circumvent the approaching bottom of Moore's law for traditional silicon based technologies. For synthesis and design new types of representations are required to exploit the full potential of these new technologies. In the past, e.g. AND-EXOR based representations have proven to be simpler than standard AND-OR representations for switching functions, while on the other hand showing many different properties. Decision diagrams have been extensively studied and have provided powerful new techniques for verification and synthesis.

The goal of the symposium is to bring together researchers in these and related fields to discuss new approaches and results. This year the symposium took place in Trier, Germany. Previous workshops have been held in Starkville, Mississippi (USA) in 2001, in Victoria, BC (Canada) in 1999, in Oxford(UK) in 1997, in Tokyo (Japan) in 1995, and in Hamburg(Germany) in 1993.

Session 1

ON SNF Optimization: A functional Comparison of Methods

Date: March 10, 2003
Language: English
Duration: 00:28:14
ON SNF Optimization: A functional Comparison of Methods

Towards a General Novel Exact ESOP Minimization Methodology

Date: March 10, 2003
Language: English
Duration: 00:16:47
Towards a General Novel Exact ESOP Minimization Methodology

An Algorithm for Optimal Presentation of a Partial Boolean Function as a MOD2 sum of products

Date: March 10, 2003
Language: English
Duration: 00:27:16
An Algorithm for Optimal Presentation of a Partial Boolean Function as a MOD2 sum of products

Session 2

Group-theoretic Approach to the Optimization Problems in Logic Design

Date: March 10, 2003
Language: English
Duration: 00:25:13
Group-theoretic Approach to the Optimization Problems in Logic Design

Reversible Logic Synthesis with Cascades of New Gate Families

Date: March 10, 2003
Language: English
Duration: 00:26:27
Reversible Logic Synthesis with Cascades of New Gate Families

Spectral Techniques for Reversible Logic Synthesis

Date: March 10, 2003
Language: English
Duration: 00:21:52
Spectral Techniques for Reversible Logic Synthesis

Session 3

BDDs, Horn Clauses and Resolution

Date: March 10, 2003
Language: English
Duration: 00:30:50
BDDs, Horn Clauses and Resolution

Minimizing AND-EXOR Expressions of Some Benchmark Functions

Date: March 10, 2003
Language: English
Duration: 00:22:41
Minimizing AND-EXOR Expressions of Some Benchmark Functions

Construction of Compact Word-Level Representations of Multiple-output Switching Functions by Wavelet Packets

Date: March 10, 2003
Language: English
Duration: 00:29:56
Construction of Compact Word-Level Representations of Multiple-output Switching Functions by Wavelet Packets

Fault Diagnosis for RAMS using WALSH Spectrum

Date: March 10, 2003
Language: English
Duration: 00:21:30
Fault Diagnosis for RAMS using WALSH Spectrum

Session 5

Totally Self-checking 1-out-of-n Checker with Applocation to Fault Tolerant Design

Date: March 11, 2003
Language: English
Duration: 00:11:24
Totally Self-checking 1-out-of-n Checker with Applocation to Fault Tolerant Design

Well-Structured Graph-Driven Parity-FBBDs

Date: March 11, 2003
Language: English
Duration: 00:26:49
Well-Structured Graph-Driven Parity-FBBDs

Variable Reordering von Parity-OBDDs

Date: March 11, 2003
Language: English
Duration: 00:33:03
Variable Reordering von Parity-OBDDs

Session 6

Multi-Output ESOP Synthesis with Cascades of New Reversible Gate Family

Date: March 11, 2003
Language: English
Duration: 00:28:07
Multi-Output ESOP Synthesis with Cascades of New Reversible Gate Family

Garbage in Reversible Designs of Multiple Output Functions

Date: March 11, 2003
Language: English
Duration: 00:23:46
Garbage in Reversible Designs of Multiple Output Functions

Reversible Function Synthesis with Minimum Garbage Outputs

Date: March 11, 2003
Language: English
Duration: 00:19:21
Reversible Function Synthesis with Minimum Garbage Outputs

Session 7/8

Binary Decision Diagrams based on Single and Multiple Generalized Shannon Expansions

Date: March 11, 2003
Language: English
Duration: 00:32:32
Binary Decision Diagrams based on Single and Multiple Generalized Shannon Expansions

Majority-Based Reversible Logic Gate

Date: March 11, 2003
Language: English
Duration: 00:17:16
Majority-Based Reversible Logic Gate

A Hierarchical Approach to Computer Aided Design of Quantum Circuits

Date: March 11, 2003
Language: English
Duration: 00:17:16
A Hierarchical Approach to Computer Aided Design of Quantum Circuits