Prof. Dr. Holger Karl

Chapter 2 (22-25)


Date: 2021-11-30
Dur: 00:35:46

Der Prozessor als Interpreter


Date: 2021-11-29
Dur: 01:28:22

Chapter 2 (Linear optimization)


Date: 2021-11-29
Dur: 00:27:22

Chapter 2 (14-21)


Date: 2021-11-26
Dur: 00:26:34

Chapter 2 (7-13)


Date: 2021-11-25
Dur: 00:21:22

Chapter 2 (5-6)


Date: 2021-11-24
Dur: 00:20:05

Chapter 2 (1-4)


Date: 2021-11-23
Dur: 00:19:12

Eingabe und Ausgabe


Date: 2021-11-22
Dur: 01:30:30

Chapter 1.4 (Queueing recap)


Date: 2021-11-22
Dur: 00:36:30

Chapter 1d (25-end)


Date: 2021-11-19
Dur: 00:27:07

Chapter 1d (19-24)


Date: 2021-11-18
Dur: 00:24:56

Register-Transfer-Ebene


Date: 2021-11-17
Dur: 01:29:01

Chapter 1d (11-18)


Date: 2021-11-17
Dur: 00:21:05

Chapter 1d (TCP CWND, 7-10)


Date: 2021-11-16
Dur: 00:41:17

Automaten & Register-Transfer-Ebene


Date: 2021-11-15
Dur: 01:29:48

Chapter 1d


Date: 2021-11-15
Dur: 00:25:44

Chapter 1d (1-4)


Date: 2021-11-12
Dur: 00:12:42

Chapter 1c (24-end)


Date: 2021-11-11
Dur: 00:43:49